Area image sensor

ABSTRACT

An area image sensor ( 1 ) includes a plurality of image pick-up elements ( 10, 20 ) arranged in a matrix including a plurality of element rows and a plurality of element columns. A plurality of signal lines (L 11 -L 14 ) are allocated to a respective one of the element columns. Each of the signal lines includes an output terminal to which an A/D converter ( 30 ) is connected. Each of the image pick-up elements belonging to the one element column is connected to only one of the signal lines, and each of the signal lines is connected to at least one of the image pick-up elements belonging to the one element column.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a CMOS area image sensor(two-dimensional image sensor) for incorporated into a digital camera,for example.

2. Description of the Related Arts

A prior art CMOS area image sensor is disclosed in JP-A 2001-36816, forexample. As shown in FIG. 1 of the gazette, the prior art area imagesensor includes a plurality of image pick-up elements arranged in amatrix. (Each of the image pick-up elements comprises a photodiode and aswitching transistor.) A vertical line of image pick-up elements iscalled a “column”, whereas a horizontal line of image pick-up elementsis called a “row”. A single signal line is provided in parallel witheach column of the image pick-up elements, whereas a single address lineis provided in parallel with each row of the image pick-up elements. Toeach signal line are connected image pick-up elements of the relevantcolumn (more precisely, output terminals of the switching transistors).To each address line are connected image pick-up elements of therelevant row (more precisely, gates of the switching transistors). AnA/D converter is connected to the output terminal of each signal line,and a shift register is connected to the output terminal of each A/Dconverter.

In the above-described area image sensor, address lines are successivelyselected one by one. Signal voltages are outputted from the imagepick-up elements of the row corresponding to the selected address lineto the A/D converters. The A/D converters compare the inputted signalvoltages with reference voltage and output digital image signals to theshift register. The shift register outputs the digital image signals insynchronization with shift pulses. (The outputted data is called “imagedata”.)

The image data for one frame is obtained when scanning of all theaddress lines is completed and respective digital image signalscorresponding to the image pick-up elements are outputted from the shiftregister. Therefore, when the frame rate is F_(R) (fps: frame/second)and the total number of the address lines is N_(A), the A/D converterneed to convert an analog signal voltage to a digital image signalwithin about 1/(F_(R)×N_(A)) second (cycle time).

Generally, a shorter cycle time causes poorer operation of the of theA/D converter. As noted above, the cycle time of the prior art sensor is1/(F_(R)×N_(A)). Therefore, when the frame rate F_(R) is increased (withthe N_(A) kept constant), there is a possibility that the A/D converterdoes not work properly.

DISCLOSURE OF THE INVENTION

An object of the present invention, which is conceived under thecircumstances described above, is to provide an area image sensor whichis capable of increasing the frame rate without hindering the stableoperation of the A/D converter.

According to a first aspect of the present invention, there is providedan area image sensor comprising a plurality of image pick-up elementsarranged in a matrix including a plurality of element rows and aplurality of element columns, a plurality of signal lines allocated to arespective one of the element columns, and a plurality of A/D convertersconnected to the signal lines, respectively. The image pick-up elementsbelonging to the one the element column is connected to only one of thesignal lines, and each of the signal lines is connected to at least oneof the image pick-up elements belonging to the one element column.

Preferably, each of the image pick-up elements comprises a photoelectricconversion element, and a switching element connected to thephotoelectric conversion element.

Preferably, two adjacent image pick-up elements belonging to the oneelement column are connected to different ones of the signal lines.

Preferably, the image sensor of the present invention further comprisesa plurality of address lines and an address line selection circuitconnected to the address lines. Each of the address lines is connectedto the image pick-up elements of a respective one of the element rows,and the address line selection circuit selects plural ones of theaddress lines simultaneously.

Preferably, the image sensor of the present invention further comprisesa shift register connected to the A/D converters.

According to a second aspect of the present invention, there is providedan area image sensor including a plurality of image pick-up elementsarranged in a plurality of columns and a plurality of rows. The areaimage sensor comprises a plurality of signal lines allocated to arespective one or two of the columns of the image pick-up elements, andA/D converters connected to the signal lines, respectively. Small groupseach consisting of successive image pick-up elements are defined in eachof the columns of the image pick-up elements, and the number of theimage pick-up elements included in each of the small groups correspondsto the number of the signal lines allocated to the column. The imagepick-up elements included in each of the small groups are connected todifferent signal lines from each other. Further, large groups eachconsisting of at least two successive small groups are defined in eachof the columns of the image pick-up elements, and in each of the largegroups, there are at least two connection patterns of the image pick-upelements to the signal lines on a small group basis.

Preferably, in each of the columns of the image pick-up elements, thenumber of the small groups included in each of the large groups ispowers of 2.

Preferably, two or more kinds of large groups differing from each otherin number of the small groups included therein are defined in each ofthe columns of the image pick-up elements.

Preferably, the image sensor of the present invention further comprisesaddress lines each of which is allocated to a respective one of the rowsof the image pick-up elements and connected to all the image pick-upelements of the row, an address line selection circuit for selectingplural ones of the address lines simultaneously, a shift register fortaking in digital signals outputted from each of the A/D converters andoutputting the digital signals through a plurality of transfer lines,and a duplexer circuit or a multiplexer circuit for switching thetransfer lines for outputting the digital signals.

Preferably, the A/D converter compares an inputted signal voltage with apredetermined reference voltage and outputs, to the shift register, acount value when the both voltages correspond to each other as a digitalsignal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a principal portion of an area imagesensor according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an image pick-up element of the imagesensor.

FIG. 3 is a block diagram of an A/D converter of the image sensor.

FIG. 4A is a time chart showing the operation timing of the A/Dconverter.

FIG. 4B is a time chart showing a comparative example relative to thepresent invention.

FIG. 5 is a time chart showing another operation timing of the A/Dconverter.

FIG. 6 is a circuit diagram showing a principal portion of an area imagesensor according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an image pick-up element of the imagesensor shown in FIG. 6.

FIG. 8 shows a connection pattern of the image pick-up elements.

FIG. 9 is a block diagram of an A/D converter used for the area imagesensor of the second embodiment.

FIG. 10 shows the operation of the A/D converter.

FIG. 11 shows signal processing.

FIG. 12 shows another signal processing.

FIG. 13 shows still another signal processing.

FIG. 14 is a circuit diagram showing a principal portion of an areaimage sensor according to a third embodiment of the present invention.

FIG. 15 shows a connection pattern of the image pick-up elements of thearea image sensor of the third embodiment.

FIG. 16A shows signal processing of a comparative example.

FIG. 16B shows signal processing in the area image sensor of the thirdembodiment.

FIG. 17 shows another signal processing in the area image sensor of thethird embodiment.

FIG. 18 is a circuit diagram showing a principal portion of an areaimage sensor according to a fourth embodiment of the present invention.

FIG. 19 shows a connection pattern of the image pick-up elements of thearea image sensor of the fourth embodiment.

FIG. 20 is a circuit diagram showing a principal portion of an areaimage sensor according to a fifth embodiment of the present invention.

FIG. 21 shows a connection pattern of the image pick-up elements of thearea image sensor of the fifth embodiment.

FIG. 22 shows a variation of the fifth embodiment.

FIG. 23 shows a connection pattern of image pick-up elements of thevariation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described belowwith reference to the accompanying drawings.

FIG. 1 is a block diagram of a CMOS area image sensor according to afirst embodiment of the present invention. The area image sensor 1 maybe used as a component of a digital camera, for example, but the presentinvention is not limited thereto.

The image sensor 1 includes a rectangular light receiving portion 1A,and the light receiving portion includes a plurality of photodiodes 10and a plurality of switching elements 20. Each of the photodiodes 10 ispaired with a respective one of the switching elements 20 to constitutea single image pick-up element. A unit area including such an imagepick-up element corresponds to one pixel. The plurality of image pick-upelements are arranged in a matrix. Each vertical line of the imagepick-up elements is called a “column”, whereas each horizontal line ofthe image pick-up elements is called a “row”.

Four signal lines Lij (i, j=1, 2, 3, . . . ) are providedcorrespondingly to each column of the image pick-up elements. Forexample, signal lines L11, L12, L13 and L14 are provided with respect tothe first column of the image pick-up elements. Each of the signal linesis connected to output terminals 20A of corresponding plural switchingelements. Similarly, signal lines L21, L22, L23 and L24 are providedwith respect to the second column of the image pick-up elements. Theoutput terminal of each signal line is connected to an analog-digitalconverter (A/D converter) 30, and the output terminal of each converter30 is connected to a shift register 40.

A single address line Ak (k=1, 2, 3, . . . ) is provided with respect toeach row of the image pick-up elements. For example, an address line A1is provided with respect to the first row of the image pick-up elements,and the address line is connected to gates 20B of corresponding pluralswitching elements. Similarly, an address line A2 is provided withrespect to the second row of the image pick-up elements. Each of theaddress lines is connected to an address line selection circuit (ASC)50.

FIG. 2 is a circuit diagram of an image pick-up element. The switchingelement 20 comprises three transistors, i.e., a reset transistor TR1, aswitching transistor TR2 and a source follower amplifier transistor TR3.The reset transistor TR1 and the switching transistor TR2 comprise CMOSdevices. A reset line is provided with respect to each row (the resetline for the first row is indicated by reference sign R1), and a commonline is provided with respect to each column (the common line for thefirst column is indicated by reference sign C1). (These lines areomitted in FIG. 1.) The reset transistor TR1 has a source, a gate and adrain which are connected to the output terminal of the photodiode 10,the reset line R1 and the common line C1, respectively. The switchingtransistor TR2 has a source, gate and a drain which are connected to thecommon line C1, the address line A1 and the source of the sourcefollower amplifier transistor TR3, respectively. The source followeramplifier transistor TR3 has a gate connected to the output terminal ofthe photodiode 10, and a drain connected to the signal line L11. Thecontact point between the drain of the source follower amplifiertransistor TR3 and the signal line L11 corresponds to the outputterminal 20A of the switching element 20, whereas the contact pointbetween the gate of the switching transistor TR2 and the address line A1corresponds to the input/output gate 20B of the switching element 20.When the switching element 20 is turned on with the gate 20B inconduction, signal charge corresponding to the received amount of lightflows from the photodiode 10 to the signal line L11, whereby signalvoltage is inputted into the A/D converter 30 through the signal line.

Now, attention is focused on the connection of the switching elements 20of the first column and the signal lines L11-L14. Every fourth switchingelement 20 of the first column is connected to a common signal line.Specifically, the output terminals 20A of the (1+4n)th switchingelements 20 (n=0, 1, 2, . . . ) are connected to the signal line L11,whereas the (2+4n) th switching elements 20 are connected to the signalline L12. The output terminals of the (3+4n)th switching elements 20 areconnected to the signal line L13, whereas the (4+4n) th switchingelements 20 are connected to the signal line L14. (Other switchingelements are connected likewise.) Technical advantages of such anarrangement will be described later.

FIG. 3 is a block diagram showing the main structure of an A/D converter30. The A/D converter 30 includes a comparator (CM) 31 and a counter(CT) 32. Signal voltage (Sv) as an analog signal is inputted into thecomparator 31 through the signal line L, while reference voltage (Rv)which increases in proportion to an operation clock (See FIG. 4A) isalso inputted into the comparator. The reference voltage is inputted ateach selection cycle (cycle time (CTM)) of the address line selectioncircuit 50. The comparator 31 compares the signal voltage Sv inputtedwithin the cycle time with the reference voltage Rv and outputs a latchsignal to the counter 32 when the both voltages correspond to eachother. The counter 32 counts the clock number. Upon receiving the latchsignal from the comparator 31, the counter 32 outputs the clock countnumber (CCN) at that time point to the shift register 40 (FIG. 1) as adigital image signal.

The shift register 40 includes a plurality of registers 41 comprisingflip-flop circuits, for example. Each of the registers 41 is connectedto the output terminal of a corresponding A/D converter 30. As will beunderstood from FIG. 1, four converters 30 and four registers 41 areprovided with respect to each column of the image pick-up elements. Theregisters 41 of the shift register 40 can be divided into four groups,and the registers 41 in the same group are connected to each other.Specifically, the registers 41 corresponding to the signal lines Li1(i=1, 2, 3, . . . ) are connected to each other. The registers 41corresponding to the signal line Li2 (i=1, 2, 3, . . . ) are connectedto each other. (Other registers are connected likewise.) After thedigital image signals are inputted from the A/D converters 30 into theregisters 41, the shift register 40 outputs the digital image signalswhile successively transferring the signals from left to right betweenthe registers 41 in synchronization with clocks, for example.

The address line selection circuit 50 selects four address lines at atime and turns on the image pick-up elements corresponding to theselected address lines. Specifically, the circuit 50 first selects theaddress lines A1-A4 and turns on the image pick-up elementscorresponding to these address lines. (As a result, signal voltage isoutputted from the image pick-up elements to the converters 30.) Then,after the cycle time CTM noted above has elapsed, the circuit selectsthe address lines A5-A8 and turns on the image pick-up elementscorresponding to these address lines. Thereafter, the selectionoperation is repeated.

Now, the entire operation of the area image sensor 1 will be describedwith reference to FIGS. 4A, 4B and 5. FIGS. 4A and 5 are time chartsshowing the operation timing of the A/D converter 30, whereas FIG. 4B isa time chart of a prior art image sensor for comparison.

First, the address line selection circuit 50 selects the first to thefourth address lines A1-A4, collectively. As a result, the switchingelements 20 of the first to the fourth rows connected to the addresslines A1-A4 are turned on. At the same time, from each of thephotodiodes 10 paired with the turned-on switching elements 20, signalvoltage produced by photoelectric conversion is supplied to the A/Dconverter 30 through the relevant one signal line (See FIG. 1).

As shown in FIG. 4A, within the cycle time CTM, each A/D converter 30compares the increasing reference voltage Rv with the signal voltage Sv.Then, the A/D converter 30 outputs, to the shift register 40, the clockcount number CCN at the time point when the both voltages correspond toeach other as a digital image signal. (This image signal is outputtedfrom the shift register 40 during when the fifth to the eighth addresslines are subsequently selected.)

After the selection of the address lines A1-A4 is finished, the firstthrough the fourth reset lines (only the reset line Rl is shown in FIG.2) are selected to reset the photodiodes 10 of the first through thefourth rows, while, on the other hand, the fifth through the eighthaddress lines are selected to perform the operation similar to theabove. By repeating such series of operation, image data for one framecorresponding to the entire light receiving portion 1A is obtained.

Now, the instance in which the frame rate is 60 fps and the total numberof address lines is N is considered. In this instance, the processingtime of each A/D converter 30 for one frame is 1/60 second. (Inpractice, a slight error is produced). Within this processing time, theA/D converter 30 performs A/D conversion N/4 times. Therefore, the timerequired for one A/D conversion (cycle time) is 1/(15×N) second. On theother hand, in the prior art method (in which a single signal line isprovided with respect to each column, and address lines are selected oneby one), A/D conversion is performed totally N times within theprocessing time for one frame ( 1/60 second). Therefore, the cycle timeis 1/(60×N) second.

In this way, according to the present invention (FIG. 4A), the cycletime is four times longer than that of the prior art method (FIG. 4B),so that the rate of change of the reference voltage within one cycletime can be reduced. As a result, provided that the operation clock ofthe A/D converter is the same, the number of bits of digital imagesignal for one pixel can be increased (i.e., the gray scale level can beincreased.) According to the present invention, the cycle time can bemade one half of that shown in FIG. 4A (See FIG. 5). By shortening thecycle time CTM, the frame rate can be increased. In this case again, thecycle time according to the present invention is longer than that of theprior art method (FIG. 4B), and the gray scale level for one pixel canbe made higher than that of the prior art method.

Further, according to the present invention, even when the operationclock of the A/D converter is set lower than that of the prior artmethod, it is possible to realize the gray scale level which isgenerally equal to or higher than that of the prior art method.Therefore, by lowering the operation clock, the power consumption by theA/D converter can be advantageously reduced.

Although a plurality of image pick-up elements are arranged in a matrixin the foregoing embodiment, the present invention is not limitedthereto. For example, the image pick-up elements may be arranged in ahoneycomb pattern. Further, five or more signal lines may be providedwith respect to each column of the image pick-up elements.

In the foregoing embodiment, the switching elements 20 connected to acommon signal line (e.g., the signal line L11) are not arranged adjacentto each other. However, the switching elements connected to a commonsignal line may be arranged adjacent to each other. Specifically, in theexample shown in FIG. 1, the switching elements 20 belonging to thefirst column (the leftmost column) may be divided into four groups(first through fourth groups) each including switching elements arrangedadjacent to each other. The switching elements 20 of the first group maybe connected to the signal line L11, the switching elements 20 of thesecond group to the signal line L12, the switching elements 20 of thethird group to the signal line L13 and the switching elements 20 of thefourth group to the signal line L14, for example. The number of groupsinto which the switching elements of each column are to be divideddepends on the number of signal lines used for the column. For example,when five signal lines are used for one column, the switching elements20 of that column are divided into five groups. In such a case, thesensor need be so designed that two or more switching elements 20belonging to the same group (connected to a common signal line) do notturn on simultaneously.

The A/D converter 30 is not limited to one which utilizes a slopingreference voltage. For example, a successive approximation converter maybe used. In this case, inputted signal voltage is successively comparedwith reference voltage produced digitally within the converter.

FIG. 6 is a block diagram of an area image sensor according to a secondembodiment of the present invention. Among the structural elements ofthe image sensor of the second embodiment, those which are identical orsimilar to the structural elements of the first embodiment are indicatedby the same reference signs as those used in the first embodiment. Thisholds true for the third through the fifth embodiments, which will bedescribed later.

As shown in FIG. 6, the area image sensor 1 including an image pick-upportion 1A includes a plurality of photodiodes 10, a plurality ofswitching elements 20, a plurality of analog/digital converters (A/Dconverter) 30, a shift register 40, an address line selection circuit50, a duplexer circuit 60, signal lines L extending vertically, andaddress lines A extending horizontally.

Each of the photodiodes 10 is connected to a respective one of theswitching elements 20 to serve as an image pick-up element. Theplurality of image pick-up elements are arranged in a matrix including aplurality of rows and columns. Two signal lines L (such as La1, Lb2) areprovided with respect to each column of the image pick-up elements. Tothe signals lines L, output terminals 20A of the switching elements 20are connected in a predetermined regular pattern. Details of the regularpattern will be described later. Each signal line L has an outputterminal connected to a respective A/D converter 30. The A/D converter30 has an output terminal connected to the shift register 40. The shiftregister 40 has an output terminal connected to the duplexer circuit 60.A single address line A (such as A1) is provided with respect to eachrow of the image pick-up elements. To each address line A, input/outputgates 20B of all the switching elements 20 of the relevant row areconnected. All the address lines A are connected to the address lineselection circuit 50.

FIG. 7 is a circuit diagram of an image pick-up element. The switchingelement 20 comprises a reset transistor TR1, a switching transistor TR2and a source follower amplifier transistor TR3. The reset transistor TR1and the switching transistor TR2 comprise CMOS devices. Though not shownin FIG. 6, a reset line R is provided with respect to each row (thereset line for the first row is indicated by reference sign R1), and acommon line C is provided with respect to each column (the common linefor the first column is indicated by reference sign C1). The resettransistor TR1 has a source, a gate and a drain which are connected tothe output terminal of the photodiode 10, the reset line R1 and thecommon line C1, respectively. The switching transistor TR2 has a source,gate and a drain which are connected to the common line C1, the addressline A1 and the source of the source follower amplifier transistor TR3,respectively. The source follower amplifier transistor TR3 has a gateconnected to the output terminal of the photodiode 10 and a drainconnected to the signal line L11. The contact point between the drain ofthe source follower amplifier transistor TR3 and the signal line La1corresponds to the output terminal 20A of the switching element 20,whereas the contact point between the gate of the switching transistorTR2 and the address line A1 corresponds to the input/output gate 20B ofthe switching element 20. In each pixel, when the switching element 20is turned on with the input/output gate 20B in conduction, signal chargecorresponding to the received amount of light flows from the photodiode10 to the signal line, whereby signal voltage is inputted into the A/Dconverter 30 through the signal line.

Now, as an example, attention is focused on the image pick-up elementsof the first column and the signal lines La1, La2, and the regularconnection pattern thereof will be described. It is to be noted that thesame regular pattern as that of the first column is applied to all othercolumns.

FIG. 8 shows the regular pattern of the first column. As shown in thefigure, the image pick-up elements P1-P32 of the first column aredivided into sub-groups (g1, g2, g3 . . . ) each of which consists oftwo image pick-up elements arranged adjacent to each other. The twoimage pick-up elements of each sub-group are connected to differentsignal lines L1 (La1), L2 (La2). Two adjacent sub-groups constitute asingle group. For example, the group G1 consists of the sub-groups g1and g2. The “OM”, “CF”, “Px” and “SL” in the figure mean the operationmode, clock frequency, pixel and signal line, respectively. Further, “1”means ON, whereas “0” means OFF.

Referring now to the group G1, the connection pattern of the sub-groupg1 to the signal lines L1, L2 differs from the connection pattern of thesub-group g2 to the signal lines L1, L2. This holds true for othergroups G2-G8. In each group, the two image pick-up elements located atthe (2n+1)th positions (n=0, 1) are connected to different signal lines.For example, in the group G1, the image pick-up elements P1 and P3 areconnected to different signal lines. In the group G2, the image pick-upelements PS and P7 are connected to different signal lines.

As shown in FIG. 8, the groups G1 and G2 constitute a parent group G#1.The parent group G#1 includes four (=2²) sub-groups (g1-g4). Similarly,the groups G3 and G4 constitute a parent group G#2, the groups G5 and G6constitute a parent group G#3, and the groups G7 and G8 constitute aparent group G#4. Further, the parent groups G#1 and G#2 constitute agrandparent group G%1. The grandparent group G%1 includes eight (=2³)sub-groups (g1-g8). Similarly, the groups G#3 and G#4 constitute agrandparent group G%2. Further, the grandparent groups G%1 and G%2constitute a great-grandparent group G&1. The great-grandparent groupG&1 includes 16 (=2⁴) sub-groups (g1-g6).

As will be understood from FIG. 8, the signal line connection pattern ofthe parent group G#1 is the same as that of the parent group G#4,whereas the signal line connection pattern of the parent group G#2 isthe same as that of the parent group G#3. However, the signal lineconnection pattern of the parent group G#1 is different from that of theparent group G#2. In the parent group G#1, the two image pick-upelements (P1 and P5) located at the (4n+1)th positions (n=0, 1) areconnected to different signal lines La1 and La2. Similarly, in theparent group G#2, the two image pick-up elements (P9 and P13) located atthe (4n+1)th positions (n=0, 1) are connected to different signal linesLa1 and La2.

Moreover, in the grandparent group G%1, the two image pick-up elements(P1 and P9) located at the (8n+1) th positions (n=0, 1) are connected todifferent signal lines La1 and La2. Similarly, in the grandparent groupG%2, the two image pick-up elements (P17 and P25) located at the(8n+1)th positions (n=0, 1) are connected to different signal lines La1and La2. Further, in the great-grandparent group G&1, the two imagepick-up elements (P1 and P17) located at the (16n+1) th positions(n=0, 1) are connected to different signal lines La1 and La2.

With such a regular pattern, in the full sampling scanning (in whichsignals are extracted from all the image pick-up elements), the twoimage pick-up elements of each sub-group (g1-g32) (such as the pair ofP1 and P2 or the pair of P3 and P4) are turned on simultaneously.Specifically, by turning on the image pick-up elements P1 and P2simultaneously, signal voltages for the first row and the second row aresimultaneously inputted into the A/D converters 30 through signal lines.Subsequently, by turning on the image pick-up elements P3 and P4simultaneously, signal voltages for the third row and the fourth row aresimultaneously inputted into the A/D converters 30 through signal lines.(Similar operation is performed with respect to other columns.) In thecase where one out of two address lines is selectively scanned (½sampling scan), the image pick-up elements P1 and P3 are simultaneouslyturned on in the group G1, whereas the image pick-up elements P5 and P7are simultaneously turned on in the group G2. In this way, signalvoltages for two rows are simultaneously inputted into the A/Dconverters 30 through signal lines.

In the case of ¼ sampling scanning, the image pick-up elements P1 and P5are simultaneously turned on in the parent group G#1, whereas the imagepick-up elements P9 and P13 are simultaneously turned on in the parentgroup G#2. Similarly, in the case of ⅛ sampling scanning, the imagepick-up elements P1 and P9 are simultaneously turned on in thegrandparent group G%1, whereas the image pick-up elements P17 and P25are simultaneously turned on in the grandparent group G%2. Further, inthe case of 1/16 sampling scanning, the image pick-up elements P1 andP17 are simultaneously turned on in the group great-grandparent groupG&1.

As shown in FIG. 9, each A/D converter 30 includes a comparator (CM) 31and a counter 32 (CT). As shown in FIG. 10, signal voltage (Sv) (plottedin the figure) which is sampled and held as an analog signal is inputtedinto the comparator 31 through the signal line, and reference voltage(Rv) which changes in the form of a slope in proportion to the operationclock (See FIG. 4A) is also inputted into the comparator 31. Thecomparator 31 compares the inputted signal voltage Sv and referencevoltage Rv and outputs a latch signal to the counter 32 when the bothvoltages correspond to each other. The counter 32 counts the clocknumber. Upon receiving the latch signal from the comparator 31, thecounter 32 outputs the clock count number (CCN) at that time point tothe shift register 40 as a digital image signal.

As shown in FIG. 6, the shift register 40 includes registers 41. Each ofthe registers 41 is connected to the output terminal of a correspondingA/D converter 30. The registers 41 are arranged in two rowscorrespondingly to the two A/D converters 30 provided with respect toeach column. The group of registers corresponding to the signal lines L1are connected to a first transfer line 42A, whereas the group ofregisters corresponding to the signal lines L2 are connected to a secondtransfer line 42B. In the shift register 40, digital image signals fromthe A/D converters 30 temporarily taken in the registers 41 aretransferred one by one through the two transfer lines 42A, 42B insynchronization with shift pulses. At this time, the duplexer circuit 60switches the transfer lines 42A, 42B at an appropriate timing inaccordance with the operation of the shift register 40. For example,when the duplexer circuit 60 is connected to the first transfer line42A, the duplexer circuit successively outputs the digital image signalson the first transfer line 42A. After the outputting is completed, theduplexer circuit 60 switches the connection to the second transfer line42B to successively output the digital image signals on the secondtransfer line 42B. In this way, digital image signals for two lines areserially outputted at the shift register 40.

Referring to FIGS. 11 through 13, the operation of the area image sensor1 will be described below. For easier understanding of the operationprinciple, it is assumed that the image pick-up portion 1A includes 16pixels i.e., four columns and four rows.

FIG. 11 shows full sampling scanning as the operation mode in which theaddress lines A1-A4 are selectively scanned one by one. It is to benoted that this mode is a comparative example and is not based on thepresent invention. FIG. 12 shows full sampling scanning in which twoaddress lines are scanned simultaneously. FIG. 13 shows ½ samplingscanning in which every other address lines are scanned two lines at atime. In each of the figures, the timing chart is shown at the upperportion, whereas the operation of the shift register is schematicallyshown at the lower portion.

As shown in FIG. 11, in the case where the address lines A1-A4 aresuccessively scanned one by one based on the address line selectionsignals ASS, the address line selection circuit 50 successively selectsthe address lines A1-A4 every time a frame signal FS (F1, F2, F3, . . .) is asserted. Herein, the “frame signal” means a signal for giving atiming to periodically take the image data for one frame. The frequencyof the frame signal corresponds to the frame rate.

When a single address line A1 is selected, the switching elements 20 ofthe first row connected to the address line A1 are turned on. At thesame time, from the photodiodes 10 paired with the turned-on switchingelements 20, signal voltages produced by photoelectric conversion aresupplied to the A/D converters 30 through the signal lines. In FIG. 11,“OD” means output data. Further, “F11” means the data outputted when theaddress line A1 is selected in accordance with the frame signal F1.Similarly, “F23” means the data outputted when the address line A3 isselected in accordance with the frame signal F2.

As shown in FIG. 10, the A/D converter 30 compares the sloping referencevoltage Rv with the signal voltage of analog input at each time ofselective scanning. Then, the A/D converter 30 outputs, to the shiftregister 40, the clock count number at the time when the both voltagescorrespond to each other as a digital image signal. The shift register40 outputs the digital image signals before a single selective scanningoperation is completed. Similarly, thereafter, the address lines A2, A3and A4 are scanned successively, and digital image signals of each roware outputted from the shift register 40 at each time of selectivescanning. Thus, one cycle of the address line selection signal ASS andoutput data shown in FIG. 11 correspond to the line scanning cycle, andthe processing for one frame is completed by four line scanning cycles.In such full sampling scanning, the A/D converter needs to perform theA/D conversion four times per one frame, so that the operation clock(clock frequency) is correspondingly set relatively high. The clockfrequency in this case is defined as “f”.

Next, the actual full sampling scanning is considered in which theaddress lines A1-A4 are scanned two at a time. (It is assumed that thecondition of the frame rate is the same as above.) In this case, asshown in FIG. 12, every time a frame signal is asserted, the addressline selection circuit 50 selects two address lines simultaneously (A1and A2, A3 and A4) for scanning.

Specifically, by first selecting the address lines A1 and A2simultaneously, the switching elements 20 of the first and the secondrows connected to the selected address lines are turned on. As a result,from the two rows of the photodiodes paired with the turned-on switchingelements 20, signal voltages are supplied to the A/D converters 30through signal lines.

The A/D converter 30 compares the reference voltage with the signalvoltage at each time of selective scanning and outputs, to the shiftregister 40, the clock count number at the time when the both voltagescorrespond to each other as a digital image signal. The shift register40 outputs the digital image signals of two rows before a singleselective scanning operation is completed. Similarly, thereafter, theaddress lines A3 and A4 are simultaneously selected, and digital imagesignals of the two rows are outputted from the shift register 40. Inthis case, one cycle of the address line selection signal ASS and outputdata shown in FIG. 12 corresponds to the line scanning cycle, and theprocessing for one frame is completed by two line scanning cycles.

This sampling scanning differs from the full sampling scanning describedbefore in that digital image signals for two rows can be obtained by asingle selective scanning operation. As another difference, as shown inFIG. 12, the duplexer circuit 60 switches the transfer lines 42A, 42B ofthe shift register 40 within the line scanning cycle, so that digitalimage signals for two rows are serially outputted through the duplexercircuit 60. The duplexer circuit 60 switches the transfer lines 42A and42B in such a manner that digital image signals can be outputted fromthe shift register 40 in the order of rows.

In this way, according to the full sampling scanning of the presentinvention, the A/D conversion by the A/D converters 30 is performedtwice per one frame. Therefore, as compared with the foregoing fullsampling scanning, the line scanning cycle can be set longer and theclock frequency can be set lower, i.e., set to about f/2.

Next, ½ sub full sampling scanning is considered on the assumption thatthe condition of frame rate is the same as above. In this case, as shownin FIG. 13, every time a frame signal F1, F2 is asserted, the addressline selection circuit 50 simultaneously selects the address lines A1,A3 corresponding to the (2n+1)th locations (n=0, 1) in the group G1 forscanning. When the two address lines A1, A3 are selected simultaneously,the switching elements 20 of the first and the third rows connected tothe address lines A1, A3 are turned on. At the same time, from the tworows of photodiodes 10 paired with the turned-on switching elements 20,signal voltages produced by photoelectric conversion are supplied to theA/D converters 30 through the signal lines L1, L2.

The A/D converter output a digital image signal to the shift register 40at each time of selective scanning. The shift register 40 outputsdigital image signals for the two rows before a single selectivescanning operation is completed. In this case, one cycle of the addressline selection signal ASS and output data shown in FIG. 13 correspondsto the line scanning cycle, so that the processing for one frame iscompleted by one line scanning cycle.

In such ½ sampling scanning, digital image signals for two rows areobtained by a single selective scanning operation. However, the obtaineddigital image signals are the data of alternate rows. Specifically, asshown in FIG. 13, the duplexer circuit 60 switches the transfer lines42A, 42B within the line scanning cycle, so that digital image signalsof alternate rows are serially outputted through the duplexer circuit60. At this time, among the digital image signals of the alternate rows,the digital image signals of the second and the fourth columns arecancelled, as indicated by hatching in FIG. 13. Therefore, from 16pixels of four rows and four columns, digital image signals for fourpixels are finally extracted, so that the amount of data for one frameis ¼ of that of the full sampling scanning.

Therefore, according to the ½ sampling scanning, the A/D conversion bythe A/D converter 30 is performed only once per one frame. Accordingly,the line scanning cycle can be set longer, and the clock frequency canbe set to f/4. Similarly, based on this operation principle, in thecases of ¼ sampling scanning, ⅛ sampling scanning and 1/16 samplingscanning, the clock frequency can be set to f/9, f/16 and f/32,respectively.

Referring again to FIG. 8, in the full sampling scanning, image data fortwo rows such as the rows of P1 and P2, the rows of P3 and P4 can beobtained at a time, so that the clock frequency can be set to f/2.

In the case of the ½ sampling scanning, the image data for the two rowssuch as the rows of P1 and P3, the rows of P5 and P7 can be obtained ata time, so that the clock frequency can be set to f/4.

In the case of the ¼ sampling scanning, the image data for the two rowssuch as the rows of P1 and P5, the rows of P9 and P13 can be obtained ata time, so that the clock frequency can be set to about f/8.

Further, by obtaining the image data for the two rows of P1 and P9 at atime and the rows of P17 and P25 at a time, the clock frequency can beset to about f/16.

In the 1/16 sampling scanning which is the lowest sampling ratio, imagedata for two rows such as the rows of P1 and P17, the rows of P33 andP49 (P33 and the subsequent elements are not shown) can be obtained at atime, so that the clock frequency can be set to about f/32.

Therefore, in the ½ sampling scanning of this embodiment, for example,the operation clock can be decreased to f/4 as compared with theoperation clock (clock frequency) f of the A/D converter in theoperation mode in which the address lines A are selectively scanned oneby one. Therefore, because of the proportional relationship between theoperation clock and the power consumption, the power consumption can beconsiderably reduced.

In the case of the ¼ sampling scanning, the operation clock can bedecreased to f/8, so that the power consumption can be further reduced.The ⅛ sampling scanning and the 1/16 sampling scanning are furtheradvantageous in terms of the power consumption.

Moreover, by appropriately adjusting the operation clock of the A/Dconverter 30 during the sampling scanning or the line scanning cycle ofthe address line selection circuit 50, both of the increased frame rateand the reduced power consumption can be realized.

FIG. 14 is a block diagram of an area image sensor according to a thirdembodiment of the present invention. In the third embodiment, foursignal lines are provided with respect to each column of image pick-upelements P. The image pick-up elements are connected to the signal linesin accordance with a regular pattern described below.

FIG. 15 shows the regular pattern of the first column according to thethird embodiment. As shown in the figure, the image pick-up elements(P1, P2, . . . ) of the first column are divided into sub-groups (g1,g2, . . . ) each of which consists of four successive image pick-upelements. The four image pick-up elements of each sub-group areconnected to different signal lines L1-L4. Two successive sub-groupsconstitute a single group. (For example, the sub-groups g1 and g2constitute a group G1.)

Referring to the group G1, the connection pattern of the sub-group g1,which is included in this group, to the signal lines L1-L4 differs fromthe connection pattern of the sub-group g2 to the signal lines L1-L4.(This holds true for other groups G2, G3, . . . ) In each group G1, G2,. . . , the four image pick-up elements (such as P1, P3, P5, P7 or P9,P11, P13, P15) located at the (2n+1)th positions (n=0, 1, 2, 3) areconnected to different signal lines L1-L4.

As will be understood from FIG. 15, in the parent group G#1, the fourimage pick-up elements (P1, P5, P9, P13) located at the (4n+1)thpositions (n=0, 1, 2, 3) are connected to different signal lines L1-L4.Similarly, in the parent group G#2, the four image pick-up elements(P17, P21, P25, P29) located at the (4n+1)th positions (n=0, 1, 2, 3)are connected to different signal lines L1-L4. Further, in thegrandparent group G%1, the four image pick-up elements (P1, P9, P17,P25) located at the (8n+1)th positions (n=0, 1, 2, 3) are connected todifferent signal lines L1-L4.

With such a regular pattern, in the case of full sampling scanning inwhich signals are extracted from all the image pick-up elements, fourimage pick-up elements such as P1-P4 or P5-P8 are turned onsimultaneously so that signal voltages for successive four rows can besimultaneously inputted into the A/D converters 30 through the signallines. In the case of the ½ sampling scanning in which one out of twoaddress lines A is selectively scanned, the image pick-up elements P1,P3, P5, P7 are simultaneously turned on in the group G1, whereas theimage pick-up elements P9, P11, P13, P15 are simultaneously turned on inthe group G2. In this way, also in the ½ sampling scanning, signalvoltages for four rows can be simultaneously inputted into the A/Dconverters 30 through the signal lines.

In the case of the ¼ sampling scanning, the image pick-up elements P1,P5, P9, P13 can be simultaneously turned on in the parent group G#1,whereas the image pick-up elements P17, P21, P25, P29 can besimultaneously turned on in the parent group G#2.

In the case of the ⅛ sampling scanning, the image pick-up elements P1,P9, P17, P25 are simultaneously turned on in the grandparent group G%1.

As shown in FIG. 14, in the shift register 40, the group of registers 41corresponding to the signal lines L1 are connected to a first transferline 42A, the group of registers 41 corresponding to the signal lines L2connected to a second transfer line 42B, the group of registers 41corresponding to the signal lines L3 connected to a third transfer line42C, and the group of registers 41 corresponding to the signal lines L4connected to a fourth transfer line 42D. Thus, the shift register 40transfers digital image signals one by one through the four transferlines 42A, 42B, 42C and 42D in synchronization with shift pulses. Atthis time, the multiplexer circuit 61 switches the four transfer lines42A, 42B, 42C and 42D at an appropriate timing in accordance with theoperation of the shift register 40. For example, the multiplexer circuit61 successively outputs the digital image signals on the first transferline 42A and then switches the connection to the second transfer line42B to successively output the digital image signals on that line.Thereafter, the multiplexer circuit switches the connection to the thirdtransfer line 42C and finally to the fourth transfer line 42D to outputthe digital image signals. With such a structure, the shift register 40outputs digital image signals for four rows serially in each row.

Next, the operation of the third embodiment will be described. Foreasier understanding of the operation principle, it is assumed that thearea image sensor includes image pick-up elements of only 48 pixelsi.e., eight rows and six columns just shown in FIG. 14 and thatperipheral circuits such as the A/D converters 30 and the shift register40 are structured correspondingly.

FIGS. 16 and 17 show the signal processing. Specifically, FIG. 16A is atiming chart of the full sampling scanning as the operation mode inwhich the address lines A1-A8 are selectively scanned one by one, FIG.16B is a timing chart of the full sampling scanning in which all theaddress lines are scanned four lines at a time, and FIG. 17 is a timingchart of the ½ sampling scanning in which every other address lines arescanned four lines at a time. It is to be noted that FIG. 16A is forcomparative reference only, and the operation mode in which the addresslines A are scanned one by one does not exist.

As shown in FIG. 16A, if the full sampling scanning in which the addresslines A1-A8 are successively scanned one by one is performed, theaddress line selection circuit 50 successively selects the address linesA1-A8 one by one every time a frame signal is asserted.

When a single address line A1 is selected for scanning, the imagepick-up elements of the first row connected to the address line A1 areturned on. At the same time, from the image pick-up elements which areturned on, signal voltages are supplied to the A/D converters 30 throughthe signal lines such as La1, Lb1.

The A/D converters 30 output digital image signals to the shift register40. The shift register 40 outputs the digital image signals before thesingle selective scanning operation is completed. Similarly, thereafter,the address lines A2, A3 and so on are successively scanned, and digitalimage signals of each row are outputted from the shift register 40 ateach time of selective scanning. Thus, one cycle of the address lineselection signal ASS and output data shown in FIG. 16A corresponds tothe line scanning cycle, and the processing for one frame is completedby eight line scanning cycles. The A/D converter needs to perform A/Dconversion eight times per one frame, so that the operation clock (clockfrequency) is correspondingly set relatively high.

Next, the inventive full sampling scanning in which the address linesA1-A8 are scanned four lines at a time is considered on the assumptionthat the condition of the frame rate is the same as above. In this case,as shown in FIG. 16B, every time a frame signal is asserted, the addressline selection circuit 50 selects the four address lines A1-A4simultaneously and the four address lines A5-A8 simultaneously forscanning.

Specifically, by first selecting the four address lines A1-A4simultaneously, the image pick-up elements P of the first through thefourth rows connected to the address lines A1-A4 are turned on. As aresult, signal voltages are supplied from the turned-on image pick-upelements P to the A/D converters 30 through the signal lines L1-L4.

The A/D converters 30 output digital image signals to the shift register40. The shift register 40 outputs the digital image signals for the fourrows before the single selective scanning operation is completed.Similarly, thereafter, the address lines A5-A8 are scannedsimultaneously, and digital image signals of four rows are outputtedfrom the shift register 40. In this case, one cycle of the address lineselection signal and output data shown in FIG. 16B corresponds to theline scanning cycle, and the processing for one frame is completed bytwo line scanning cycles.

This sampling scanning differs from the full sampling scanning describedbefore in that digital image signals for four rows can be obtained by asingle selective scanning operation. Further, since the multiplexercircuit 61 switches the transfer lines 42A, 42B, 42C, 42D of the shiftregister 40 within the line scanning cycle, digital image signals forfour rows are serially outputted through the multiplexer circuit 61. Themultiplexer circuit 61 switches the transfer lines 42A, 42B, 42C, 42D insuch a manner that digital image signals from the shift register 40 canbe outputted in the order of rows. For example, in the stage in whichthe image signals for the first four rows are outputted (i.e., theaddress lines A1-A4 are selectively scanned), the transfer lines areswitched in the order of 42A, 42B, 42C, and 42D. In the stage in whichthe image signals for the next four rows are outputted (i.e., theaddress lines A5-A8 are selectively scanned), the transfer lines areswitched in the order of 42B, 42C, 42D, 42A. According to the fullsampling scanning, the A/D conversion by the A/D converters 30 isperformed twice per one frame. Therefore, the line scanning cycle can beset long, and the clock frequency can be set lower than that of theforegoing full sampling scanning, i.e. set to about f/4.

Next the ½ sub full sampling scanning is considered on the assumptionthat the condition of the frame rate is the same as above. In this case,as shown in FIG. 17, every time a frame signal is asserted, the addressline selection circuit 50 simultaneously selects address lines A1, A3,A5, A7 corresponding to the (2n+1)th locations (n=0, 1, 2, 3) in thegroup G1 for scanning.

When the four address lines A1, A3, A5, A7 are scanned simultaneously,the image pick-up elements P of the first, the third, the fifth, and theseventh rows connected to the address lines A1, A3, A5, A7 are turnedon. At the same time, signal voltages are supplied from the turned-onimage pick-up elements P to the A/D converters 30 through the signallines L1-L4.

The A/D converters 30 output digital image signals to the shift register40 at each time of selective scanning. The shift register 40 outputsdigital image signals for the four rows before a single selectivescanning operation is completed. In this case, one cycle of the addressline selection signal and output data shown in FIG. 17 corresponds tothe line scanning cycle, and the processing for one frame is completedby one line scanning cycle.

In such ½ sampling scanning, digital image signals for four rows areobtained by a single selective scanning operation. However, the obtaineddigital image signals are the data for alternate rows. In the shiftregister 40, the multiplexer circuit 61 switches the transfer lines inthe order of 42A, 42C, 42B, 42D within the line scanning cycle, so thatdigital image signals of alternate rows are serially outputted throughthe multiplexer circuit 61. At this time, among the digital imagesignals of the alternate rows, the digital image signals of the second,the fourth and the sixth columns are cancelled. Therefore, from 48pixels of eight rows and six columns, digital image signals for 12pixels are finally extracted, so that the amount of data for one frameis ¼ of that of the full sampling scanning.

Therefore, according to the ½ sampling scanning of the third embodiment,the A/D conversion by the A/D converter 30 is performed only once perone frame. Therefore, the line scanning cycle can be set longer, and theclock frequency can be set to about f/8. Similarly, in the cases of ¼sampling scanning and ⅛ sampling scanning, the clock frequency can beset to about f/16 and f/32, respectively.

Next, a fourth embodiment will be described. FIG. 18 is a block diagramof an area image sensor according to the fourth embodiment. The areaimage sensor of the fourth embodiment is suitable for color imaging.Each of image pick-up elements is provided with a filter of either oneof three primary colors RGB. Specifically, the image pick-up unitindicated by phantom lines and including image pick-up elements of tworows and two columns provides one pixel. For example, in each pixel, thecolor filter for the upper left image pick-up element is G, that for theupper right one is R, that for the lower left one is B and that for thelower right one is G, for example. In such a structure, each of theimage pick-up elements is called a “sub-pixel”. Thus, one pixelcorresponds to four sub-pixels.

In the fourth embodiment, the number of signal lines L for each columnis the same as that of the third embodiment (i.e., four signal lines).However, the fourth embodiment differs from the third embodiment in theconnection pattern of the signal lines and the image pick-up elements.

FIG. 19 shows the connection pattern of the image pick-up elements(sub-pixel SPX) of the first column according to the fourth embodiment.The group structure of the image pick-up elements of the fourthembodiment is the same as that of the third embodiment. As will beunderstood from the figure, there are only two patterns of signal lineconnection for the sub-groups (g1, g2, . . . ). Specifically, theconnection pattern for each of the sub-groups g1, g4, g6 and g7 is[L1→L2→L3→L4]. On the other hand, the connection pattern for each of thesub-groups g2, g3, g5 and g8 is [L3→L4→L1→L2]. With such a structure, ineach group G1, the four image pick-up elements located at the (4n+1)thpositions and the (4n+2)th positions (n=0, 1) are connected to differentsignal lines L1-L4. Specifically, in the group G1, the image pick-upelements P1, P2, P5, P6 are connected to different signal lines L1-L4.In the group G2, the image pick-up elements P9, P10, P13, P14 areconnected to different signal lines L1-L4.

Further, in each of the parent groups G#l and G#2, the four imagepick-up elements located at the (8n+1)th positions and the (8n+2) thpositions (n=0, 1) are connected to different signal lines L1-L4.Specifically, in the group G#1, the image pick-up elements P1, P2, P9,P10 are connected to different signal lines L1-L4, whereas, in the groupG#2, the image pick-up elements P17, P18, P25, P26 are connected todifferent signal lines L1-L4. Further, in the grandparent group G%1, thefour image pick-up elements (P1, P2, P17, P18) located at the (16n+1)thpositions and the (16n+2)th positions (n=0, 1) are connected todifferent signal lines L1-L4.

With such a regular pattern, the operation in the full sampling scanningin which signals are extracted from all the image pick-up elements isthe same as that in the third embodiment. In the ½ sampling scanning inwhich one out of two address lines A is selectively scanned, the imagepick-up elements located at the first, the second, the fifth and thesixth positions are simultaneously turned on in each of the groups G1,G2, . . . . In this way, also in the ½ sampling scanning, signalvoltages for four rows can be simultaneously inputted into the A/Dconverters 30 through signal lines.

In the case of the ¼ sampling scanning, the image pick-up elementslocated at the first, the second, the ninth and the tenth positions ineach of the parent groups G#1 and G#2 (P1, P2, P9, P10 and P17, P18,P25, P26) can be simultaneously turned on.

In the case of ⅛ sampling scanning, the image pick-up elements 1P1, P2,P17, P18 located at the first, the second, the seventeenth, and theeighteenth positions in the grandparent group G% are turned onsimultaneously. In this way, also in the ½ sampling scanning, the ¼sampling scanning and the ⅛ sampling scanning, signal voltages for fourrows can be simultaneously inputted into the A/D converters 30 throughsignal lines L.

In the case of the full sampling scanning, the address selection circuit50 selectively scans four address lines (A1-A4 or A5-A8) simultaneouslyfor conduction. In the ½ sampling scanning, while grouping into the unitof groups such as G1, G2, the address line selection circuit selectivelyscans four address lines (A1, A2, A5, A6) corresponding to the (4n+1)thand the (4n+2)th positions (n=0, 1) in each group G1, G2 simultaneouslyfor conduction. In the case of the ¼ sampling scanning, the address lineselection circuit 50 selectively scans four address lines (referencesigns omitted) corresponding to the (8n+1)th and the (8n+2)th positions(n=0, 1) in each parent group G#1, G#2 simultaneously for conduction. Inthe case of the ⅛ sampling scanning, the address line selection circuit50 selectively scans four address lines (reference sign omitted)corresponding to the (16n+1)th and the (16n+2)th positions (n=0, 1) inthe grandparent group G%1 simultaneously for conduction. Thus, in any ofthe ½ sampling scanning, the ¼ sampling scanning and the ⅛ samplingscanning, four address lines A can be simultaneously turned on at eachtime of selective scanning.

Next, the operation of the fourth embodiment will be described. It is tobe noted that the operation timing is the same as that of the thirdembodiment shown in FIGS. 16 and 17.

As the operation mode of the fourth embodiment, the ½ sub full samplingscanning is considered on the assumption that the frame rate is the sameas the full sampling scanning. In this case, every time a frame signalis asserted, the address line selection circuit 50 simultaneouslyselects address lines A1, A2, A5, A6 corresponding to the (4n+1)thpositions and the (4n+2)th positions (n=0, 1) in the group G1 forscanning.

When the four address lines A1, A2, A5, A6 are selected simultaneously,the image pick-up elements P of the first, the second, the fifth, andthe sixth rows connected to the address lines A1, A2, A5, A6 are turnedon. At the same time, signal voltages are supplied from the turned-onimage pick-up elements P to the A/D converters 30 through the signallines L1-L4.

The A/D converters 30 output digital image signals to the shift register40. The shift register 40 outputs digital image signals for the fourrows before a single selective scanning operation is completed.Thereafter, the similar operation is repeated with respect to the unitof the group G2. Therefore, similarly to the third embodiment, theprocessing for one frame is completed by one line scanning cycle in such½ sampling scanning. The amount of data for one frame becomes ¼ of thatof the full sampling scanning. The operation clock (clock frequency) ofthe A/D converter 30 can be set to about f/8.

Based on the same operation principle as that of the third embodiment,in the cases of the ¼ sampling scanning and the ⅛ sampling scanning, theclock frequency can be set to about f/16 and f/32, respectively.

In the ½ sampling scanning, image data for four rows connected todifferent signal lines L1-L4 such as the rows P1, P2, P5, P6 or the rowsP9, P10, P13, P14 can be obtained at a time, so that the clock frequencycan be set to about f/8.

In the ¼ sampling scanning, image data for four rows such as the rowsP1, P2, P9, P10 or the rows P17, P18, P25, P26 can be obtained at atime, so that the clock frequency can be set to about f/16.

In the ⅛ sampling scanning which is the lowest sampling ratio, imagedata for four rows connected to different signal lines L1-L4 such as therows P1, P2, P17, P18 or the rows P33, P34, P49, P50 (P33 and thesubsequent rows are not shown) can be obtained at a time, so that theclock frequency can be set to about f/32.

A fifth embodiment will be described below.

FIG. 20 is a block diagram of an area image sensor according to thefifth embodiment of the present invention. Similarly to the area imagesensor of the fourth embodiment, the area image sensor of the fifthembodiment is suitable for color imaging. Color filters of the threeprimary colors RGB are arranged in the same pattern similar as thatshown in FIG. 18. The image pick-up elements (sub-pixels) of two rowsand two columns indicated by phantom lines provide one pixel.

In the fifth embodiment, eight signal lines are provided per twocolumns. (The number of signal lines for one column is four.)

FIG. 21 shows the regular pattern of the first column of the fifthembodiment. The group structure of the fifth embodiment is the same asthat of the fourth embodiment. Referring to the entirety of the firstcolumn, there are four connection patterns of the image pick-up elementsof sub-groups (such as g1, g2) with respect to the signal lines L1-L8.Of the four connection patterns, two are the patterns for the signallines L1-L4 only, whereas the remaining two are the patterns for thesignal lines L5-L8 only. Therefore, in each of the groups (such as G1,G2), the four image pick-up elements located at the (4n+1)th positionsand the (4n+2)th positions (n=0,1) such as the image pick-up elementsP1, P2, P5, P6 or P9, P10, P13, P14 are connected to different signallines (L1-L4, L5-L8), while corresponding to either of the group ofsignal lines L1-L4 and the group of signal lines L5-L8.

Further, the image pick-up elements P1, P2, P9, P10 located at the(8n+1)th positions and the (8n+2)th positions (n=0, 1) in the parentgroup G#1 are connected to different ones of the signal lines L1-L8,whereas the image pick-up elements P17, P18, P25, P26 located at the(8n+1)th positions and the (8n+2)th positions (n=0,1) in the parentgroup G#2 are connected to different ones of the signal lines L1-L8.

In the grandparent group G%1, the four image pick-up elements (P1, P2,P17, P18) located at the (16n+1)th positions and the (16n+2)th positions(n=0,1) are connected to different signal lines L1-L4.

As shown in FIG. 20, as for the entirety of the columns, the oddcolumns, i.e., the first and the third columns have the same connectionpattern, while the even columns, i.e., the second and the fourth columnshave the same connection pattern. Further, the connection patterns ofthe first and the second columns are symmetrical, while the connectionpatterns of the third and the fourth columns are also symmetrical.

With such a regular pattern again, the same operation as that of thefourth embodiment can be performed. Therefore, in any of the ½ samplingscanning, the ¼ sampling scanning and the ⅛ sampling scanning, signalvoltage for four rows can be simultaneously inputted into the A/Dconverters 30 through appropriate four of eight signal lines L1-L8.

In the full sampling scanning, image data for four rows such as the rowsP1-P4 or the rows P5-P8 constituting each sub-group can be obtained at atime, so that the clock frequency can be set to about f/4.

In the ½ sampling scanning, image data for four rows connected todifferent signal lines L1-L8, such as the four rows P1, P2, P5, P6 orthe four rows P9, P10, P13, P14 can be obtained at a time, so that theclock frequency can be set to about f/8.

In the ¼ sampling scanning, while grouping into the parent groups G#1,G#2, image data for four rows connected to different signal lines L1-L8,such as the four rows of P1, P2, P9, P10 or the four rows of P17, P18,P25, P26 can be obtained at a time, so that the clock frequency can beset to about f/16.

In the ⅛ sampling scanning which is the lowest sampling ratio, imagedata for four rows connected to different signal lines L1-L4, such asthe four rows of P1, P2, P17, P18 or the four rows of P33, P34, P49, P50(P33 and the subsequent rows are not shown) can be obtained at a time,so that the clock frequency can be set to about f/32.

As a variation of the fifth embodiment, the structure as shown in FIGS.22 and 23 may be employed.

In the variation again, eight signal lines are provided per two columns,and the number of signal lines for one column is four. Unlike the fifthembodiment, each pair of image pick-up elements facing each other areconnected to adjacent signal lines. Therefore, in each of the groupssuch as G1, G2, the four image pick-up elements located at the (4n+1)thpositions and the (4n+2)th positions (n=0, 1) (such as P1, P2, P5, P6 orP9, P19, P13, P14) are connected to different signal lines from eachother (L1, L3, L5, L7 or L2, L4, L6, L8), while corresponding to eitherof the group of odd signal lines L1, L3, L5, L7 and the group of evensignal lines L2, L4, L6, L8.

As for the parent groups G#1 and G#2, the four image pick-up elements(P1, P2, P9, P10 or P17, P18, P25, P26) located at the (8n+1)thpositions and the (8n+2)th positions (n=0, 1) in each of the parentgroups are connected to different signal lines L1-L8 from each other.

Further, in the grandparent group G%1, the four image pick-up elements(P1, P2, P17, P18) located at the (16n+1)th positions and the (16n+2)thpositions (n=0, 1) are connected to different signal lines L1, L3, L5,L7.

With such a connection pattern again, an operation similar to that ofthe fifth embodiment can be performed.

In the case of color imaging, the color filter provided for each imagepick-up element may comprise a complementary color filter for colorseparation into YMC and G.

The present invention being thus described, it is apparent that the samemay be varied in many ways. Such variations should not be regarded as adeparture from the spirit and scope of the present invention, and allsuch modifications as would be obvious to those skilled in the art areintended to be included within the scope of the following claims.

1. An area image sensor comprising a plurality of image pick-up elementsarranged in a matrix including a plurality of element rows and aplurality of element columns; a plurality of signal lines allocated to arespective one of the element columns; and a plurality of A/D convertersconnected to the signal lines, respectively; wherein each of the imagepick-up elements belonging to said one of the element columns isconnected to only one of the signal lines, and wherein each of thesignal lines is connected to at least one of the image pick-up elementsbelonging to said one of the element columns.
 2. The sensor according toclaim 1, wherein each of the image pick-up elements comprises aphotoelectric conversion element, and a switching element connected tothe photoelectric conversion element.
 3. The sensor according to claim1, two adjacent image pick-up elements belonging to said one of theelement columns are connected to different ones of the signal lines. 4.The sensor according to claim 1, further comprising a plurality ofaddress lines and an address line selection circuit connected to theaddress lines, wherein each of the address lines is connected to theimage pick-up elements of a respective one of the element rows, andwherein the address line selection circuit selects plural ones of theaddress lines simultaneously.
 5. The sensor according to claim 1,further comprising a shift register connected to the A/D converters. 6.An area image sensor including a plurality of image pick-up elementsarranged in a plurality of columns and a plurality of rows, the areaimage sensor comprising: a plurality of signal lines allocated to arespective one or two of the columns of the image pick-up elements; andA/D converters connected to the signal lines, respectively; whereinsmall groups each consisting of successive image pick-up elements aredefined in each of the columns of the image pick-up elements, the numberof the image pick-up elements included in each of the small groupscorresponding to the number of the signal lines allocated to the column,the image pick-up elements included in each of the small groups beingconnected to different signal lines from each other; wherein largegroups each consisting of at least two successive small groups aredefined in each of the columns of the image pick-up elements, andwherein, in each of the large groups, there are at least two connectionpatterns of the image pick-up elements to the signal lines on a smallgroup basis.
 7. The area image sensor according to claim 6, wherein, ineach of the columns of the image pick-up elements, the number of thesmall groups included in each of the large groups is powers of
 2. 8. Thearea image sensor according to claim 6, wherein, two or more kinds oflarge groups differing from each other in number of the small groupsincluded therein are defined in each of the columns of the image pick-upelements.
 9. The area image sensor according to claim 6, furthercomprising address lines each of which is allocated to a respective oneof the rows of the image pick-up elements and connected to all the imagepick-up elements of the row, an address line selection circuit forselecting plural ones of the address lines simultaneously, a shiftregister for taking in digital signals outputted from each of the A/Dconverters and outputting the digital signals through a plurality oftransfer lines, and a duplexer circuit or a multiplexer circuit forswitching the transfer lines for outputting the digital signals.
 10. Thearea image sensor according to claim 6, wherein the A/D convertercompares an inputted signal voltage with a predetermined referencevoltage and outputs, to the shift register, a count value when the bothvoltages correspond to each other as a digital signal.